Field programmable logic arrays (FPLA) are used on a regular basis for implementing and testing prototype circuits. Currently, a variety of different FPLA's are available commercially for use in design and testing. A typical FPLA includes a plurality of logic elements arranged in rows and columns, and an interconnect system for coupling electrically the various logic elements to cause the logic elements to cooperate to perform a desired function. In a typical FPLA, the interconnect system connects logic elements in a "flat" manner, that is, the interconnect system connects all of the logic elements in the same manner, without providing for structured division of the logic elements into blocks of elements.
The prior art FPLA's, although functional, have a number of significant drawbacks. These drawbacks stem mostly from the fact that the logic elements are interconnected in a substantially flat manner, and thus have no structured hierarchy. To elaborate, most circuit designs are preferably implemented in a hierarchical manner. To implement these circuit designs on conventional FPLA's, a hierarchy is created. Since the FPLA's are not themselves hierarchically structured, the hierarchy is implemented by way of the interconnect system. Creating a hierarchy using the interconnect system is not problematic when the circuit to be implemented is relatively simple; but when the circuit is not simple, very complex interconnection schemes can result.
These complex interconnection schemes, in turn, may lead to several significant problems. First, complex interconnection schemes make it very difficult to predict whether a particular FPLA will be able to implement a specific circuit. While an FPLA may have the proper number of logic elements, the interconnect resources may be insufficient to implement the desired design. It is difficult to determine, without actually implementing the design, whether the FPLA can support the implementation. This means that a user, given a circuit design, cannot determine confidently at the outset whether the circuit can actually be implemented by the FPLA. Thus, uncertainty is injected into the design process. Second, the uncertainty inherent in complex routing schemes makes it difficult to predict the routing delays imposed on signals by the interconnections. In applications where the timing of signals is critical, the FPLA may be precluded from being used to emulate the circuit. As an additional problem, the interconnection complexity increases geometrically with the number of logical elements involved in the implementation. Thus, for very complicated circuits, the prior art FPLA's may not be usable at all in the design process. In light of the shortcomings discussed above, there exists a need for an improved FPLA structure.